The invention relates to a buffer, for example for a contact card. The invention is particularly related to a contact card using a power supply potential VDD1 different from a power supply potential VDD2 used by a reader with which the card communicates.
A contact card C1 (FIG. 1) generally comprises an integrated circuit CI grouping together all the electronic circuits capable of performing all the functions of the card. The circuit CI is connected to at least one contact pad or terminal PAD. When the card is used, the contact terminal/terminals of the card come into contact with one of the corresponding terminals of the card reader into which the card is inserted. A pad or terminal PAD can be used as input terminal for the circuit CI to receive data coming from the reader C2 or as output terminal so that the circuit CI can transmit data to the reader. A same terminal PAD can also be used as input terminal for certain functions of the circuit CI and as output for other functions of the circuit CI.
When the card power supply potential VDD1 is different from the reader power supply potential VDD2, then an input and/or output buffer has to be used between the terminal PAD and the circuit CI of the card to adapt the amplitude of the signals. An input buffer BE thus has the function of converting signals received from the reader, which range from 0 to VDD2, into signals ranging from 0 to VDD1 that can be exploited by the circuit CI. Similarly, an output buffer BS has the function of converting signals to be transmitted to the reader and ranging from 0 to VDD1 into signals ranging from 0 to VDD2 that are exploitable by the card reader.
When a terminal PAD is used as input and output, the input and output buffers should not disturb each other at the common point at the terminal PAD. To this end, in particular, the output buffer BS should have a high impedance output when it is not used. In one example, we consider a card powered by an internal power supply potential VDD1 powering the card. This potential VDD1 is lower than the potential VDD2 powering the reader. The internal power supply potential VDD1 powering the card is produced, by a known regulation circuit, from the potential VDD2 received at an input of the card. An input buffer for a card of this kind is made according to known approaches using, in particular, inverters supplied with the potential VDD1. An output buffer for a card of this kind is shown in FIG. 2. It includes two potential step-up circuits 10, 20 and one tristate inverter 30.
The potential step-up circuit 10 receives a logic control signal VAL that takes either of two values, 0 or VDD1, and it produces a logic signal HVAL of a higher level, taking two values:
HVAL=0 when VAL=0
HVAL=VDD2 when VAL=VDD1.
In the example of FIG. 2, the potential step-up circuit 10 comprises two P type transistors T1, T3, two N type transistors T2, T4, and one simple inverter I1 powered by VDD1. The transistors T1, T2 are series-connected. The potential VDD2 is applied to the source and the well of T1 and the source of T2 is connected to a ground of the circuit. The common drain of the transistors T1, T2 is connected to the gate of T3. The transistors T3, T4 are also series-connected. The potential VDD2 is applied to the source and the well of T3, and the source of T4 is connected to the ground of the circuit. The common drain of the transistors T3, T4 is connected to the gate of T1 and forms the output of the potential step-up circuit 10 at which the signal HVAL is produced. Finally the gate of T2 is connected to the gate of T4 via the inverter I1. The gate of T2 forms the input of the step-up circuit to which the signal VAL is applied.
The step-up circuit 20 receives a logic signal DATA, taking either of two values, 0 or VDD1, and it produces a logic signal INT that is the inverse of the signal DATA but has a higher level. The signal INT thus takes two values:
INT=VDD2 when DATA=0
INT=0 when DATA=VDD1.
The step-up circuit 20 is made in the same way as the step-up circuit 10; a simple inverter I2 powered by the potential VDD2 has simply been added to the output of the step-up circuit 20. The inverter 30 receives the validation signal HVAL and the data signal INT, which take either of two values, 0 or VDD2. The inverter 30 has an output terminal OUT connected to the terminal PAD of the card. The inverter 30 works as follows: it produces a logic signal HDATA that is the inverse of INT, e.g. the same logic value as DATA, at the output OUT when the signal HVAL is active (in the example equal to 0); its output OUT is at high impedance when the signal HVAL is inactive.
The inverter 30 has two P type transistors T5, T6, two N type transistors T7, T8 and one simple inverter I3. The transistors T5, T6, T7, T8 are series-connected between a ground of the circuit and a power supply terminal to which the potential VDD2 is applied. The potential VDD2 is applied to the wells of the transistors T5, T6 and to the source of the transistor T5 whose drain is connected to the source of T6. The source of T8 is connected to the ground of the circuit and its drain is connected to the source of T7. The drains of the transistors T6, T7 are connected together to the output OUT of the inverter 30. The gates of the transistors T5, T8 are connected together and receive the signal INT. Finally, the gate of T6 is connected to the gate of T7 via the inverter I3 powered by VDD2. The gate of T6 receives the control signal HVAL.
The inverter 30 works as follows. When HVAL=VDD2, the transistors T6, T7 are off and the output OUT is at high impedance, whatever the value of INT and whatever the state of the transistors T5, T8. Conversely, when HVAL=0, the transistors T6, T7 are on. Depending on the value of the signal INT, the transistor T5 or the transistor T8 is on and the logic signal HDATA, which is the inverse of the signal INT, is produced at the output OUT. The signal HDATA is finally identical to the signal DATA from a logic point of view, but is at a higher potential level. It must be noted that the signals HVAL and INT must necessarily reach the value VDD2 to turn off the operation of the inverter 30, and more specifically to turn off the transistor T6, whence the necessity of using the potential step-up circuits 10, 20.
The buffer of FIG. 2 has the drawback of using a large number of transistors. Indeed, given that a simple inverter (like I1, I2 or I3) is made from a P type transistor and an N type transistor that are series-connected, it is necessary to use a total of 20 transistors to make the buffer. The fact that the number of transistors is large naturally entails a large-sized circuit, and also substantial power consumption.
It is an object of the invention to make a buffer with a reduced number of transistors, to make a buffer that is smaller-sized and consumes less power than the prior art buffers having the same function.
This and other objects are attained by a buffer according to the invention that includes a logic gate to raise the potential level of input digital data having a first logic level (xe2x80x9c1xe2x80x9d) to a potential equal to a low power supply potential (VDD1), and to produce intermediate data if a validation signal is active. The intermediate data has a first logic level (xe2x80x9c1xe2x80x9d) whose potential is equal to a high power supply potential (VDD2), and the intermediate data is logically inverse to the input data. The buffer also includes a tristate inverter to produce output data, at an output, that are logically inverse to the intermediate data if the validation signal is active and having its output OUT at high impedance if this is not the case.
A buffer according to the invention has the same function as a prior art equivalent buffer: at its output, it produces data which, from a logic point of view, is identical to the data that it receives at its input but has a different potential level. However, the buffer according to the invention uses only one potential step-up logic gate and therefore uses a far smaller number of transistors than a prior art buffer, and shall be seen more clearly here below in examples.